Queen’s University Biology Department

Position Transducer


Principle of Operation

The position transducer can be divided into the following sections:

·         master clock oscillator

·         transmitting amplifier

·         two receive channels


Each receive channel can be further divided:

·         differential input amplifier

·         synchronous detector


U7A and U7B form a simple relaxation oscillator, with a frequency in the range 30kHz to 100kHz.  The exact frequency is unimportant.


The master clock is amplified by U8, and out J7, the “wand” connector, where it connects to a radiating antenna.  This antenna typically takes the form of a thin piece of copper wire (approx. #42 gauge), secured along the wing of the insect.


The signal transmitted from the wand is received by the “- and “+ receiving antennae of each channel (channel 1: J1 J2; channel 2: J4, J5).  Typically, the two channels will frame the insect wing such that their axes are perpendicular, thus capturing the two-dimensional position of the wand.


The signals from the “+“ and “-” antennae are differentially amplified by the AD620 instrumentation amplifiers (U1, U4).  Differential amplification rejects any 60Hz hum or other common-mode interference that may have been picked up by the antennae.  The differential amplification results in an output from the AD620 which is a copy of the original transmitted signal, but whose amplitude and polarity are determined by the relative position of the wand between the “+” and “-“ antennae.


The amplitude and polarity of the received waveform are finally converted into a DC voltage by a synchronous detector circuit.  This circuit works by sampling the instantaneous voltage of the signal at the same instant in each clock cycle, and holding that voltage until the next clock cycle.  This function is performed by the very easy-to-use AD781 sample-and-hold chip.


U9A and U9B (both one-shots) generate the gate-pulse driving the sample-and-hold chips.  U9A is triggered at the start of each clock cycle, and resets after a fixed delay.  This specifies the instant at which the synchronous detector latches the received instantaneous voltage.  U9B is triggered by U9A, and generates a very short pulse, just long enough to drive the sample-and-hold chips.  U9A is tuned (by R24) to position the gate-pulse at the peak of the received signal.  This results in the greatest output voltage range.  (Actually, it should be tuned for the negative peak, to counter the inversion of the output by U8.)


The output of the sample-and-hold chips are low-pass filtered to remove any of the master clock that may leak through.